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        1、培訓過程中，如有部分內(nèi)容理解不透或消化不好，可免費在以后培訓班中重聽；
        2、培訓結(jié)束后,授課老師留給學員聯(lián)系方式,保障培訓效果,免費提供課后技術(shù)支持。
        3、培訓合格學員可享受免費推薦就業(yè)機會。

培訓方式以講課和實驗穿插進行。

Description:

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This is an Engineer Explorer course for designers familiar with Static Timing Analysis (STA). This course does not teach the basics of STA. See the Prerequisites section.

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This course is a detailed exploration of the timing and signal integrity analysis capabilities of the Encounter?? Timing System. You explore static timing analysis, signal integrity analysis with crosstalk coupling, and IR drop and multi-supply/multi-voltage (MSMV) effects that are inherent in advanced process nodes with feature sizes 90 nm and below. It is necessary to analyze these effects and take them into account in advanced process designs to insure the highest probability of first silicon success. An introduction to SSTA (Statistical Static Timing Analysis)is included as a new feature starting with the 7.1 release.

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Learning Objectives

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In this course, you?
●?? Review static timing analysis concepts?
●?? Run timing analysis and apply basic debugging approaches?
●?? Study interconnect crosstalk effects and analysis principles?
●?? Run crosstalk analysis and practice debugging methods?
●? Study power supply IR drop and MSMV effects on timing and signal integrity?
●? Setup Multi-Mode Multi-Corner (MMMC) analysis?
●? Perform some advanced Tcl scripting

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Software

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Encounter? Timing System

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Agenda

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Unit 1

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●? Introduction?
●? Timing Analysis Concepts?
●? Timing Analysis Lab?
●? Crosstalk and Signal Integrity Analysis?
●? Noise Library Characterization Lab?
●? Crosstalk Analysis Lab?
●? Power Supply IR Drop and MSMV Analysis?
●? IR Drop/MSMV Lab

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Unit 2

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●? Advanced Topics?
●? MMMC Lab?
●? Advanced Tcl Scripting Lab
●? Wrap-up

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Audience:

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●?? CAD Engineers
●?? Place and Route Designers
●?? IC Designers
●?? Digital IC Designers
●?? Design Engineers
●?? Chip Designers